1. Field of the Invention
This invention relates to a packet processor, and more particularly to a packet processor which is suitable for use in a packet router for executing various packet processes, to update a packet header
2. Description of Related Art
Nowadays, with a spread usage of network for inter-terminal communications, there is an increased necessity of interconnecting networks, such as between LANs (Local Area Network) via an LAN and a leased line. Most of the networks currently in operation are those by the IP (Internet Protocol).
The IP is a communication protocol of connectionless type corresponding to the network layer of the OSI (Open System Interconnection) layer model of the ISO (International Organization for Standardization). The communication between terminals using the IP (IP communication), unlike the connection-type protocol, which secures a communication route between the terminals in advance, is realized by routing a packet in which communication data is stored based on the destination information (destination IP address) through the packet router interconnecting LANs.
When a packet is routed in the IP network, packet processing, such as calculating a check sum of a packet header, retrieving the destination table and updating a packet header, is required. Further, the IP network is also necessary to be equipped with a packet filter, which restricts the communication on the network. Since executing such processes employing dedicated hardware is too complicated, the processing are usually executed by software.
FIG. 18 of accompanying drawing is a block diagram schematically showing a conventional packet router. The packet router 100 includes packet receiving/processing units 101 and packet transmitting/processing units 103 as many as the connected networks (LANs 104 in FIG. 18). The packet router 100 is also equipped with a switch fabric (switching unit) 102 which guides a packet received in the packet receiving/processing unit 101 to a desired packet transmitting/processing unit 103.
When a packet is routed by the packet router 100, a packet received by the receiving interface 111 of the packet receiving/processing unit 101 is temporarily stored into a memory 112 via a bus 114. Then calculating the check sum, retrieving the destination table and updating the header of the packet stored in the memory 112 are executed by the packet processor 113 (hereinafter also called the processor).
The received packet having updated information, such as destination information decided by the packet processing of the processor 113, is transmitted to the switch fabric 102 via the bus 114. The received packet is further transmitted to a transmitting interface 131 of an appropriate transmitting/processing unit 103 by the switch fabric 102 in accordance with the decided destination information, and then the transmitting interface transmits the packet to the destination LAN 104. In this manner, the packet router 100 routes a packet received from the desired LAN 104 to the destination LAN 104 based on the destination information of the packet.
The packet processing performed by the processor 113 will now be described in detail. FIG. 19 is a block diagram focused on the memory 112 and the packet processor 113. The packet processor 113 includes an external bus interface 121, an external bus buffer 122, a general-purpose arithmetic operator 123, a general-purpose register 124, a program counter 125, a flag register 126, and a controller 127.
The external bus interface 121 is used for interfacing with the bus 114, and packet data is transferred between the processor 113 and the memory 112 via the external bus interface 121. The external bus buffer 122 is used for temporarily storing received packet data to be packet processed in future. The general-purpose operator 123 performs various arithmetic operations, such as an integer number arithmetic operation, a logical arithmetic operation, and a bit arithmetic operation, in accordance with an instruction input from an instruction decoder 128 of the controller 127. These various arithmetic operations result in transferring, comparing and arithmetic-operating of the packet data.
The general-purpose register 124 (composite of sixteen registers r0 through r15) is used for storing received packet data and retaining source data to be arithmetic-operated and results of arithmetic operations. Selectors 124a, 124b, which are respectively disposed in opposite sides of the general-purpose register 124, select a source register from which the data is output (extracted), or a destination register to which data is input in the general-purpose register 124 (r0 through r15).
The program counter 125 retains the position of an instruction, which is currently executed, in a program, and increments its counts one by one in response to the execution of individual instructions. The flag register 126 evaluates the result of arithmetic operation performed in the general-purpose arithmetic operator 123. The controller 127 decodes instructions, which are input via the external bus interface 121, (by the instruction decoder 128) to give control signals to individual components of the processor 113. The instructions may be retained in the memory 112, which stores received packets, or in a dedicated external memory.
In the above-mentioned processor 113, the received packet data is read from the memory 112 to transfer to the general-purpose register 124 in accordance with a data-transfer instruction from the controller 127 (instruction decoder 128). Then the processor 113 performs a series of the packet processing, such as retrieving the destination table, calculating the header check sum and updating the destination address of the packet header, on the packet data stored in the general-purpose register 124 in accordance with an instruction from the controller 127 (the instruction decoder 128).
At that time, the processor 113 extracts a particular field (such as the TTL (Time To Live) field), whose bit length is not limited to the same as that of the general-purpose register 124 (32 bits in the illustrated example), from an arbitrary register ri (i is an integer number between 0 and 15), and the extracted particular field is stored into another register ri as work memory where packet processing is executed. After the packet processing on the particular field, the particular field is written into the source register ri, as the last part of the series of the packet processing, in units of the bit length of the general-purpose register 124.
Then the packet processor 113 transfers the updated packet data stored in the general-purpose register 124 back to the memory 112 when a demand arises, and properly transmits a processed packet to the switch fabric 102 from the memory 112 via the bus 114. The processor 113 stores received packets in the general-purpose register 124 to repeatedly perform extraction and writing of the particular fields, and updates the packet fields. As a result, appropriate packet processing can be realized using the processor 113.
As the modern networks increase in capacity and speed, higher-speed packet routing process is demanded. However, since the bit length (alignment) of a packet field to be processed does not always match with the bit length of the general-purpose register 124, the above-mentioned processor 113 cannot perform the packet processing at high speed.
Assuming that the general-purpose register 124 has a bit length of 32 bits and the packet format is the Ethernet format as shown in FIG. 20, the processor 113 stores the IP address (SA (Source Address) of 32 bits or DA (Destination Address) of 32 bits) of 32 bits separately into the two succeeding registers ri, 16 bits each, as the packet header is stored into the general purpose-register 124. When the packet processor 113 executes a field extraction process, which extracts particular field from the packet data stored in the general-purpose register 124, and also a field write process in accordance with a data-transfer instruction, the processor 113 has to perform a shift arithmetic operation and a mask arithmetic operation, which updates the field except for the particular field to xe2x80x9c0xe2x80x9ds, in the arithmetic operator 123 in addition to transferring data from the memory 112. As a result, the shift arithmetic operation and the mask arithmetic operation require extra clock cycles so that the conventional processor 113 cannot execute high-speed packet processing with ease, which has been demanded by the modern networks.
As one solution, there is an idea of executing a high-speed packet processing employing a dedicated hardware circuit. However, such dedicated hardware circuit cannot easily keep up with a revise of protocols and change of functions aimed for an improvement service as a network. Further, another dedicated hardware circuits are required so as to manage each of such revises and changes.
On the contrary, the processor 113 performs the packet processing consulting with instructions, i.e. software (programs). Therefore the processor 113 has high flexibility such as to easily cope with a revise of protocols and a change of functions aimed for an improved service as a network after the processor has been completely structured. The high-speed extraction/writing of a packet field taking great advantage of the flexibility of the processor 113 is indispensable for high-speed routing.
With the foregoing problems in view, it is an object of the present invention to provide a high-flexibility packet processor, which can execute extraction and write processes of a packet field at high speed in accordance with software (instructions).
To attain the above object, according to a first generic feature of the present invention, there is a packet processor comprising: a general-purpose register for retaining packet data; a general-purpose arithmetic operator for performing a predetermined general-purpose arithmetic operation on a particular field of the packet data, which is retained by the general-purpose register, in accordance with a general-purpose arithmetic operation instruction; a dedicated field extracting circuit for performing a field extraction process of extracting information of the particular field from the general-purpose register as object field information, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator, in accordance with a field extraction instruction; and a dedicated field writing circuit for performing a field write process of writing a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field in accordance with a field write instruction.
With the above-mentioned packet processor, since the dedicated circuit extracts information of the particular field from packet data stored in the general-purpose register and writes a result of arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field in accordance with the instructions, the extraction process and write process of the particular field, which is an object for the processes by the general-purpose arithmetic operator, can be performed at high speed. As a result, a packet processor having high flexibility using instructions and high-speed performance can be realized.
As a preferable feature, the dedicated field extracting circuit and the dedicated field writing circuit may be in the form of a shared composite circuit dedicated to field extraction and field write, which result in an decreased size in the circuit scale.
As another preferable feature, the packet processor may comprise an instruction retaining section for retaining a field-extraction-and-field-write bit pattern, which represents a bit position of the particular field in the general-purpose register, and a bit rotation extent of the particular field in the general-purpose register as a composite instruction, and the shared composite circuit dedicated to field extracting and field writing may be operative to perform the field extraction process and the field write process based on the composite instruction retained in the instruction retaining section. With the packet processor having this preferable feature, since a shift arithmetic operation and a mask arithmetic operation of the particular field, likewise the conventional packet processor, do not have to be performed, field extraction and field write processes can be performed in higher speed.
As still another preferable feature, the instruction retaining section and the general-purpose register may be in the form of a composite register for retaining both the composite instruction and the packet data. With this composite register, an instruction to the particular field does not have to be designated and retained in a dedicated register by the name thereof different from the name of another register retaining the packet data. As a result, programming efficiency can be improved because of the shorter-length of an instruction and less storage area for retaining instruction.
As a further preferable feature, the general-purpose arithmetic operator and the shared composite circuit, which is dedicated to field extracting and field writing, may be (1) individually operated in accordance with two different programs separately describing unique procedures associated with the respective dedicated instructions, (2) operated in accordance with a shared program collectively describing unique procedures associated with the respective dedicated instructions, or (3) operated in accordance with a shared program describing unique procedures associated with a composite instruction that includes an instruction dedicated to field extracting/writing and also an instruction dedicated to an arithmetic operation.
In the case of the two different programs ((1)) since the arithmetic operation and field extraction/write processes can be performed completely in parallel, it is possible to execute the packet processing at extremely high speed.
In the case of the shared program collectively describing unique procedures associated with respective instructions ((2)), since the circuit components, such as a program counter, can be shared to reduce the quantity of the components, it is also possible to reduce the circuit scale.
In the case of the shared program describing unique procedures associated with a composite instruction ((3)), partly since the arithmetic operation and field extraction/write process can be performed in parallel and partly since the circuit components can be shared to reduce the quantity of the components, it is possible to realize a high-speed packet processor having an reduced size in the circuit scale.
As a still further preferable feature, the shared composite circuit, which is dedicated to field extracting and field writing, shares a component of the general-purpose arithmetic operator, it can operate in accordance with a shared program collectively describing unique procedures associated with the respective dedicated instructions.
With this shared composite circuit, it is possible to further reduce the size of the packet processor can be further reduced, and at the same time, to increase the rate of the packet processing.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.